ICLAB 12 : Post-Layout Simulation ( IRSIM )
( Tape-out verification : Dracula DRC/ERC/LVS ) 

Before You Start 

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IRSIM is an event-driven logic-level simulator with MOS transistor delay modeling. 

The commands of IRSIM are list in the course text book. In the file named counter.cmd in the path ~cadlabt3/NDL/lab9 has some simple testing commands. 



Demo item 

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We use IRSIM to run the post-layout simulation and verification of demo program counter of lab.7. To check the logic function is correct or not. 

After that, we can run the tape-out verification Dracula DRC/ERC/LVS 



Task Flow [ I ] 

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< IRSIM simulation >


To obtain the Hspice "netlist" file of program counter from extract view. 
(without pads, like lab.6 steps) 

In the "netlist" file directory, key in command : 
~cadlabt3/techfile/s2s_06 netlist 

It will transform the "netlist" file to IRSIM input format files : 

netlist.sim 
netlist.node 
(3) In UNIX system , key in alias command : 

alias irsim 'irsim ~cadlabt3/techfile/tsmc06.prm \!*.sim' 
tsmc06.prm is the MOS delay modeling file of IRSIM 
IRSIM simulation command : 
irsim netlist 

IRSIM will compile the "netlist.sim" file 

(5) Give commands of IRSIM to check the logic function of the design. 

@ counter.cmd 
To see the simulation waveform result 



Task Flow [ II ] 

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< Dracula verification >


Copy the following files to your account : 

~cadlabt3/dracula/drc-06spdm.com 
(Dracula DRC/ERC execution command file for tsmc 0.6um process) 

~cadlabt3/dracula/lvs-06spdm.com 
(Dracula LVS execution command file for tsmc 0.6um process)


1. RUN Dracula DRC/ERC : 


1) Generate xx.gds file : 

stream out action: 


CDS.log window 下 

--> Translators 

--> Physical 

--> Stream out 


Library name : mulccd 

Top cell name : mul 

Output File : xx.gds 

--> option 

--> case sensitivity 

--> preserve 


產生xx.gds file 


2) RUN Dracula DRC : 

drc-06spdm.com file needed to modify:


INDISK=~/b/mul.gds ( 欲作dracula drc之gds file 所在處 ) 

PRIMARY=mul ( top cell name for the layout ) 

OUTDISK=mul.out ===> 產生之debug file 為mul.out 

PRINTFILE=mul ===> report file : mul.sum


cadlabt3>PDRACULA 

: /g drc-06spdm.com 

: /f 

　 ===> 產生 jxrun.com execution file


cadlabt3>jxrun.com 

===> 產生xx.sum 之 report file


對包含pad之layout, stream out之GDS file作Dracula DRC/ERC 
input pin -----> xx:S 

output pin -----> xx 

power supply -----> VDD: , VSS: (for both vdd/gnd of core and pads) 

用TEXT dg layer ,create--->label打在該 pins 上 


2. Run Dracula LVS


1) Generate xx.cir file : 

CDLOUT action:


CDS.log window 下 

--> Translators 

--> netlist 

--> CDLOUT


TOP cell name : mul 

view name : schematic 

library name : mulccd 

output file : xx.cir 

run directory : ~/......... 


產生xx.cir file


3) RUN Dracula LVS: 

lvs-06spdm.com file needed to modify: 


INDISK=~/b/mul2.gds (欲作Dracula LVS 之xx.gds file 所在處) 

PRIMARY= mul (top cell name for the layout) 

OUTDISK=mul.out ==> 產生之debug file 為 mul.out 

PRINTFILE=mul ==> report file : mul.lvs


cadlabt3> LOGLVS 

: htv 

: cir xx.cir (CDLOUT 之 xx.cir file) 

: con xx (top cell name of the CDLOUTs schematic view) 

: x 

===> 產生 LVSLOGIC.DAT file



cadlabt3>PDRACULA 

: /g lvs-06spdm.com 

: /f 

===> 產生 jxrun.com execution file


cadlabt3>jxrun.com 

===> 產生 xx.lvs report file


對不包含 pad 之layout, stream out 之GDS file作 Dracula LVS 
input pin -------> xx 

output pin -------> xx 

power supply -------> vdd! , gnd! 


用 "TEXT" dg layer, create ---> label 打在該 pins 上 


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Exercise :


You can use the exercise result of lab.8 to go through the IRSIM simulation and verification. 

There are Dracula DRC/ERC/LVS verification result in the following paths : 

Dracula DRC/ERC result : ~cadlabt3/dracula/drc 
Dracula LVS result : ~cadlabt3/dracula/lvs 

It is a 8 bits program counter design.